Altera NIOS II soft processor has been known as the world’s most versatile embedded processors. What is the reason behind since in my opinion the CPU architecture is more or less the same compared with other processors? In my opinion, the unsung hero that contributes to the success of the NIOS II processor is the Avalon Switch Fabric. I find it a bit weird that Altera or distributors does not put very much effort in directly marketing the Avalon Interface Specification introduced by Altera years ago. I strongly believe that the user-friendly Avalon Interface is one of the main reasons engineers choosing NIOS II processor over their main rival’s Xilinx MicroBlaze processor. It doesn’t matter whether you are designing a master or slave peripheral, as long as your own-designed peripheral supports Avalon Interface, your peripheral can communicate with others peripheral, including NIOS II processor flawlessly as the Avalon Switch Fabric will handle the communication for you.
The Avalon Switch Fabric is generated by Altera SOPC Builder that comes together with Quartus II software tool. That means after installing Quartus II, you do not need to worry about installing the SOPC Builder as it is part of Quartus II software. I like this because I don’t like to open a few application softwares at the same time doing one job. Another good point to mention about the SOPC Builder is the evaluation is free and valid for unlimited period. You just have to re-apply a new Quartus II web edition license about every three months through internet and the license will be sent to your email in split seconds. Too bad that the newly-announced NIOS II C-to-Hardware Acceleration (C2H) Compiler is not available for evaluation to the public without going through the Altera distributors. I am very curious with the improvement achieved using the C2H compiler.
Although many free peripherals that support Avalon interface are available, such as SDRAM controller, DDR SDRAM controller, interval timer, DMA module, UART, etc, it is still very critical to be able to connect your custom IP to the Avalon Switch Fabric. You will find yourself in a situation at times where you need to complete a lot of intensive calculation work within a very short period of time in FPGA. Some good examples are carrying out blemish test for a camera module and CRC checking for a large amount of data. Most of the time, the intensive calculation part takes too much time in C and therefore you can design your own IP in HDL to achieve the performance needed. The purpose of the new C2H compiler is to help the software designers who are not familiar with HDL to accelerate the software functions in their systems. I don’t know how good they are yet without evaluation but I truly believe that if you know HDL, you are still the best person to do the parallel processing in hardware for yourself.
The Avalon Interface uses very easy-to-understand signal types, such as chipselect, read, write, address, clock, reset, readdata, writedata, etc and you can expect yourself to get comfortable with this standard within a day or two. The latest feature that was added to Altera Avalon Interface Specification is Burst Transfer, which is very useful when maximum throughput is required. Burst Transfer guarantees that arbitration between the Avalon Master-Slave pair locked throughout a burst until the burst completes.
Many engineers misunderstand that Avalon Switch Fabric is meant for FPGA devices. Guess what, the CPLD device such as MAX II also supports Avalon Interface. For an example, you can design your custom IP, say a SDRAM master that reads and writes to a SDRAM device that connects to your MAX II device. The setup in the SOPC Builder is as shown in the figure beside. Anyway, NIOS II processor is not supported in MAX or MAX II device as I believe the NIOS II architecture requires on-chip memory.
Recently, due to some reasons, I was required to migrate a NIOS II design to a MicroBlaze design. Unfortunately, there are so many different interface buses involved when I look at the MicroBlaze data sheet, such as On-Chip Peripheral (OPB) bus, Local Memory Bus (LMB) and Fast Simple Link (FSL) bus, just to name a few. I believe it is going to take me quite some times to go through all these new bus standards. No wonder Altera claims that the NIOS II soft processor is the world’s most versatile embedded processor. Well, I think they are right.
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