C or HDL in FPGA?

There are always two options to create one design in FPGA, first through HDL and second through C language. Many FPGA beginners always ask me whether they should design their IPs in HDL or C in the FPGA. HDL, a.k.a Hardware Description Language, refers to the well-known verilog HDL or VHDL language whereas C in this article refers to the common C or C++ programming language.

If your IP needs very fast performance, it is best to design it with HDL because the design is in RTL (Register Transfer Level) and you know exactly how many clock cycles taken to transfer data among all the registers. You also define and create all the state machines needed in your IP. Using HDL, you can create as many parallel processing as possible to improve your design performance. The downside when designing with the HDL is it always takes more development and debugging time than designing with the C. Sometimes, simulation is required to make sure the HDL design behaves as expected at the targeted operating frequency.

You probably learn C language earlier than HDL in your life. So, needless to say, you most probably feel more comfortable when creating your IP in C. Besides, it always takes less development time and much easier to debug as most C compiler provides a user-friendly debugging platform. The disadvantage for C is that you can’t control much about the timing performance. You usually don’t know or you don’t even bother how much time taken to execute one function in your design. The most critical downside of C language is that you can’t do parallel processing. Everything works in serial with C, except when the DMA (Direct Memory Access) is called to work. The most you can do with C is code optimization and use the DMA as frequent as possible.

Although there are pros and cons for both design entry with HDL and C, you can actually combine both in your IP to optimize your IP performance as well as to shorten the time taken for your IP to market. For the design portion that needs critical performance, design it with HDL. On the other hand, for the design portion that requires many processing, design it with C to save some development time and also your limited logic resource in the FPGA.

In the digital world, many people refer the engineers who do their designs using HDL as Hardware Engineer whereas the engineers who write C code as Software Engineer. Many hardware-software integration issues appear due to the clear line drawn between the Hardware Engineer and Software Engineer. Due to this reason, I hate to call myself as either one of them because for me, both are just equally important.

There is a very good article that talks about the issues raised when integrating hardware and software. Feel free to read the interesting “When Hardware Met Software” from Xilinx. This is the reason I love Xilinx, they keep on publishing interesting and useful articles for public for FREE!