Thursday, July 06, 2017

Quartus II Synthesis Error During Compilation

If you are seeing the following error message and wondering what is wrong with your System Verilog syntax, then, you have come to the right place.  I believe you are using dual dimensional input and/or output in the module port list like shown in the template below.  The truth is there might be nothing wrong with your code, you just need to add the System Verilog file into the Quartus II project. 

module SubModule
  input                   clk,
  input                   reset,
  input[15:0]          input_port[0:3],
  output reg[15:0]  output_port[0:3]

To add this file to your Quartus II project, simply go to Project menu and choose “Add/Remove Files in Project…”.  The rest of the steps should be quite straight forward for you.  Just choose the file and add it in the project.  Then, recompile your Quartus II project.  After that, this synthesis error will disappear.  Before doing this step, if you right-click on the error message and choose Help, it will show you the Quartus II help like the shown in the link below but to me this help content doesn’t help at all.

I need to write this down to keep reminding myself not to fall into the same trap again.  Sometimes, it could just take hours to realize about this.  As far as I know, this happens to the latest Quartus II version 17.0 (latest as of today) and also earlier Quartus II versions.

Here is the synthesis error message displayed in the Quartus II message window.

ID:10703 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance "<string>" because the instance has no module binding

Hope this helps you.

Tuesday, June 16, 2015

Any Replacement For Altera EPCQ Devices?

I previously wrote an article “Any Replacement For Altera EPCS Devices?” in year 2006.  I hope it has helped a lot of engineers out there.  This article serves the same purpose.  I just want to raise the same awareness here especially if this is your very first time using Altera FPGAs.  You can confidently replace the expensive EPCQ devices with N25Q serial flash from Micron.  The price difference is really huge!  Look at price table below.  I don’t even need to elaborate more.  Prices are quotated from Digikey or Newark website as of today.
Altera Part Number
Price (USD$)
Micron Part Number
Price (USD$)

Besides the cost difference, there is a huge advantage by using N25Q128 or N25Q064.  Their packages are both SOIC-8 whereas EPCQ64 and EPCQ128 are only available in SOIC-16 packages as of today.  This could save you some board space!

I personally had tested N25Q128A13ESE40E and N25Q256A13EF840E on hardware to configure Altera FPGAs in both Active Serial x4 and Active Serial x1 modes.  It works fine.  No issue for the Quartus II software programmer to program the POF files into these N25Q devices, too.

Friday, February 28, 2014

Function '__builtin_stwio' could not be resolved

If you are using Eclipse IDE for Altera NIOS II C++ firmware development, you will probably be annoyed by the following two reported semantic error messages when you are using IOWR() and IORD() macros from the io.h:
Function '__builtin_stwio' could not be resolved for IOWR() functions in the C++ code.
Function '__builtin_ldwio' could not be resolved for IORD() function in the C++ code.

Anyway, you will still be able to load and run the firmware program in the hardware successfully and everything is working as expected.

These two error messages (builtin stwio could not be resolved and builtin ldwio could not be resolved) are however do not appear if you convert your C++ code to C code. 

But you want to write your code in C++.  The question is how to remove the two reported semantic error messages above because they are very annoying and they keep distracting you from the actual error messages?

Simple.  Go to the Windows in main menu bar.  Select Preferences.  On the left-hand column, expand C/C++.  Select Code Analysis.  Scroll down a bit on the right-hand column.  Look for the option Function cannot be resolved.  Then, it is up to you to change this setting.  You can uncheck the option for Function cannot be resolved.  Or, you can just change it to Info or Warning from the drop-down list.

Important reminder, after applying the change of the setting, don’t forget to close the Eclipse IDE and reopen it.  I noticed that without restarting the Eclipse IDE, the new setting is not effective.  After restarting the Eclipse IDE, you will notice that the two semantic error messages above are no longer reported as error.

Monday, October 21, 2013

Cyclone V needs Windows 64-bit

Seeing Cyclone V architecture is almost like a dream comes true, at least for me.  If you told me that this will be the Cyclone V architecture ten years ago, I would laugh at you right away, “Are you sure you are not talking about Stratix?”

By the way, your fear is true, Quartus II compilation for Cyclone V FPGA device requires Windows 64-bit OS.  I had tried to compile a few designs targeting Cyclone V FPGA using a 32-bit Windows 7 Professional laptop with 4Gbytes memory, it all ended with failure due to out of memory.  In fact, one of the designs was a relatively small design with around 1800 logic elements using the smallest Cyclone V GX device 5CGXFC3BF7F23C8.

Anyway, this is not a nightmare.  You just need to plan ahead by preparing yourself a PC with Windows 64-bit OS if you are serious in using any Cyclone V device in your new design. 

Well, compiling a simple 32-bit counter won’t crash, though.

Wednesday, April 14, 2010

Quartus II 9.1 and NIOS II 9.1 on Windows 7

I am sharing my personal experience here. I have been using Quartus II 9.1 and NIOS II IDE 9.1 on Windows 7 since they were released. Now, I am using Quartus II 9.1 SP2 and NIOS II IDE 9.1 SP2.

A lot of users were asking questions the compatibility of these softwares on Windows 7.
Quartus II 9.1 and its SOPC builder seem to work fine on Windows 7 since the first day they are installed.

It is the NIOS II IDE 9.1 that really bothered me. Most of the time when you build a project, it will report error messages like two examples below. The success rate is only 20%.

Example 1:
make -s all includes
3 [main] ? (3732) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x9E0000, top 0xB30000, reserve_size 1372160, allocsize 1376256, page_const 4096
2 [main] make 7588 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make: vfork: Resource temporarily unavailable

Example 2:
make -s all includes
3 [main] ? (4980) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x970000, top 0xA40000, reserve_size 847872, allocsize 851968, page_const 4096
2 [main] make 1972 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make[1]: /cygdrive/c/altera/91/nios2eds/components/altera_hal/build/ fork: Resource temporarily unavailable
3 [main] ? (6092) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x970000, top 0xA60000, reserve_size 978944, allocsize 983040, page_const 4096
8408744 [main] make 1972 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make[1]: /cygdrive/c/altera/91/nios2eds/components/altera_hal/build/ fork: Resource temporarily unavailable
make[1]: *** No rule to make target `/bin/gtf/', needed by `system_description/../obj/'. Stop.
make: *** [system_project] Error 2
Build completed in 40.947 seconds

Some says it is related to the Norton Antivirus software. Yes, my PC is installed with Norton Antivirus software. But I observed that it happened to Windows 7 PC which is not installed with Norton Antivirus software, as well. Turning off the Norton Antivirus software does slightly help to increase the probability that the project is successfully built, from 20% to about 40%.

Anyway, I found some tricks which can make your life easier if you are using Nios II IDE 9.1 on Windows7.

Under your Quartus II folder, go to bin->cygwin->bin folder, select the following files in the list below and then right-click and choose Properties. Under the Compatibility tab, check Run this program in compatibility mode for:” and choose “Windows XP (Service Pack 2)”. Check “Run this program as an administrator”, as well.
Here is the list of files that you can select to change their compatibility mode under the Quartus II->bin->cygwin->bin folder:
1. Make.exe
2. Sh.exe
3. Echo.exe
4. Cygstart.exe
5. MakeInfo.exe
6. Perl.exe

7. Collect2.exe (under nios2eds\bin\nios2-gnutools\ H-i686-pc-cygwin\libexec\gcc\nios2-elf\3.4.6)
8. Nios2-elf-g++.exe (under nios2eds\bin\nios2-gnutools\ H-i686-pc-cygwin\bin)

By doing the steps mentioned above, the success rate of building a project in NIOS II IDE 9.1 will be increased to above 90%.

Friday, October 03, 2008

When your Altera USB-Blaster is not working ...

When your USB-Blaster is not working and you have verified that it is neither USB Driver issue nor PCs issue nor USB cables issue, there is no need to feel disappointed, frustrated and throw away the USB Blaster which worth USD$300 market value yet.

There is still hope to salvage your USB Blaster. You can try to replace both the MAXIM low-voltage level translator parts (part number: MAX3378E) on the small USB-Blaster board. Usually, I found that both the MAXIM parts need to be replaced when I came across a bad USB-Blaster. Their reference designators on the small USB-Blaster board are labeled U2 and U5, respectively.

Alternatively, if you can’t find the MAXIM parts, you can use Texas Instruments 4-bit bidirectional voltage-level translator with part number TXS0104EPWRG4. It works equally fine and slightly cheaper, too.

Thursday, September 06, 2007

Thick Film Resistor vs Thin Film Resistor

If you are a system designer, you probably always find that there are two kinds of chip resistor, which are thick film resistor and thin film resistor. The question is, what is the difference between thick film resistor and thin film resistor?

Found this site that explains the difference.

Saturday, March 31, 2007

Cyclone series continues ...

Finally, Altera launched Cyclone III, after a couple of months lauching Stratix III. Of course, success stories should be continued... That's why we still see Cyclone III and Stratix III today.

To be honest, I anticipated improvement on the Cyclone III logic elements architecture compared with Cyclone II, such as implementing a 5-input LUT in a logic element. Nonetheless, other improved features are pretty interesting, too. I am particularly excited with M9K, PLL reconfiguration and improved I/O element.

The cost is an important factor when you are evaluating a new device. However, the cost factor is never mentioned in the data sheet or handbook. I am referring to Digikey for cost comparison among all the Cyclone series families. EP3C25 is chosen as benchmark as it is the only Cyclone III FPGA available now. The Cyclone II and Cyclone FPGAs that come closest to this density are EP2C20 and EP1C20, respectively. No doubt, from the table below, Cyclone III is certainly worth considered if you have a new design to start with a low-cost FPGA. At a slightly lower price, you can get a higher performance, same density and twice internal memory size for Cyclone III FPGA, compared with Cyclone II and Cyclone I.

Cyclone series








Low power consumption seems to be the highlight for Cyclone III in the Altera marketing slides. Unfortunately, that doesn’t interest me too much as I am not working very much on the portable designs. Anyway, I still hope to use 65-nm Cyclone III and Stratix III parts for my new coming designs.

Saturday, October 14, 2006

Can PLL self-locked without "External" input?

I was busy working on something and suddenly a crazy idea came up.

Can a PLL lock itself if I connect a PLL output clock to the PLL input clock on a PCB and both the PLL multiplication and division value is set to 1? I expected the answer is no, of course. But the curiosity kills sometimes. So, I went ahead and did the simple test.

I was using a Cyclone II device. Surprisingly, I saw the PLL locked output signal went high. However, the output signal frequency wasn't the expected frequency (10MHz). I probed at the PLL output clock (which was also connected to the PLL input clock signal), it showed about 420kHz.

So, what is the conclusion of this story? Nothing.

Saturday, September 02, 2006

Lattice Now Blogs!

Insteresting! Lattice now blogs! A lots of non-confidential-but-technical information out there!
It is always nice to see a FPGA vendor takes initiative to provide a platform for their knowledgable engineers to share their experience and knowledge. The good thing is that the knowledge shared is not only limited to Lattice products but all the vendors FPGA.
I know it is not easy for the writers as they now have one more repeatitive task in their long to-do list besides their daily jobs. Anyway, I hope they continue doing this! Bravo to all the writers!

Tuesday, August 01, 2006

Embed Tclet in Your HTML

Since started this blog, I found out that I need to study a minimum amount of HTML to display my writing correctly. Besides, I can have more control writing in "HTML mode" compared with "Compose mode". For an example, you can't just type the symbol "<" in your blog message, instead, you need to type "&lt;" to display "<" in your blog. Don't get me wrong, I am not trying to show off my HTML skills. In fact, I only have very basic and minimum knowledge about HTML.

Anyway, if I am not wrong (considering myself not a webmaster), it seems like HTML alone doesn't have the ability to let you do real-time programming stuff on your web browser, such as Mozilla Firefox or Internet Explorer. However, it can be done using a plugin.

There are many different types of plugins out there, but I choose to use Tcl applet or Tclet since I did some study on this language before. (If you've never heard of the Tcl/Tk language before, you can visit here.) I don't know how to embed a Tclet properly in blogspot. However, I manage to do it on another free site. This Tclet in this free site is to display all the gray code counter results in sequence after you have entered the number of bits your gray code counter is. I don't know how useful it is to you, but it is useful to me because I always forget how the gray code counter increments. Bear in mind that if you are a first-time user or viewer, you need to download and install the Tcl Web Browser Plugin for free. And, of course, it is SAFE to be installed in your PC. If you haven't installed it yet, you will see a blank square instead of the picture on the left side here.

It will be a bit long for me to describe how to embed Tclet in your HTML code here. The best source is the reference book that I show in here. Of course, you can look at the HTML code in the example above. Plenty of funky Tclet examples can also be easily found on web if you are interested to see others. Hope you like it.

Thursday, July 13, 2006

Save More Power In Handheld Devices

How to save more power when your CPLD device is in idle mode?
Use a very slow clock to reduce toggle rate? Partially disabling the logic inside the device? Well, why not powering off the device?
I came across this interesting article by accident and found it a simple yet smart idea to prolong the battery life of a portable handheld devices. In future, if I have the chance to design a portable product with interactive user interface, this idea will surely be the first one to cross my mind.
If for whatever reason, you have to use a FPGA in a battery-operated product, this article will sure help you more.

Sunday, July 02, 2006

OP-AMP Configurations Recall

It has been a while since I last dealed with op-amp. So, it is good to recall some of the most fundamental op-amp configurations, especially when I am dealing with them recently.
In my opinion, op-amp is like logic gates in analog world. You need op-amps to transfer your analog inputs into your desired analog outputs.
The following are some important notes for me, not for you, of course, :)!

Common NamesOp-Amp CircuitsTransfer Functions
Voltage Follower AmplifierVout = Vin
Inverting AmplifierVout = -(Rf/Rs)Vin
Noninverting AmplifierVout = (1+R2/R1)Vin
Difference AmplifierIf R1/R2 = R3/R4,
Vout = (Vin+ - Vin-)(R2/R1) + Vshift
Summing AmplifierVout = (R2/R1)* (V1+V2-V3-V4)

Sunday, June 04, 2006

Embedded Logic Analyzer inside FPGA

There is no reason to doubt that most of the FPGA users like you and me have gone through some painful experiences wanting to know what is happening inside an FPGA. It is even more painful when you strongly believe your code is working fine and you don’t have any clue which part of the design is causing you sleepless nights. You keep on routing all the suspected internal signals to the very limited unused I/O pins of your FPGA and then probe and trigger them on your oscilloscope that usually has only four channels or LESS! Sad to say, the oscilloscope couldn’t help much in situation like this unless it is related to the signal integrity issue.

If you are lucky, you can have a logic analyzer instrument to sample a lot of signals for your analysis and verification. Well, if you are not, good news for you, you can insert an embedded logic analyzer inside your FPGA and it is totally licensed-free, at least for Altera FPGA users! The Altera Embedded Logic Analyzer tool named SignalTap II is FREE for use even you don’t purchase any software license from Altera. That means you can use your SignalTap II inside Quartus II Web Edition software for FREE provided that you install and enable the TalkBack Feature of Quartus II software.

The SignalTap II works almost like a logic analyzer equipment but at a very much smaller scale as it has very limited on-chip memory to store the sampled data. Other logic analyzer’s features such as Rising-Edge triggering, Falling-Edge triggering, Either-Edge triggering, Boolean triggering, Multi-Level triggering and others are also available in the SignalTap II tool. In fact, you can also instantiate up to 127 SignalTap II instances in your design, as long as it can fit in your chosen FPGA device. You can imagine each instance of SignalTap II is a small scale of logic analyzer equipment which also has an external trigger-in and trigger-out. And, the input of the trigger-in can come from other instances trigger-out or I/O pins or any internal logic signal. I think this is an advantage to the SignalTap II because a logic analyzer equipment trigger-in must come from one of your device I/O pins, isn’t it? Anyway, I rarely make use of the trigger-in, trigger-out and the multiple analyzer features because I prefer to monitor all my signals in just one analyzer. Why bother creating so many instances of analyzer where it doesn’t help saving you any logic and memory resource at all? One of the reasons is you need to have different acquisition clocks for the signals that you are interested to tap. It could also be you have different sample depth requirement for your acquiring signals and etc.

The purpose of this post is not to teach you using SignalTap II, but to make you aware of the availability of this tool if you haven’t come across or heard of this tool. My life as a FPGA user would have been a lot easier if I learnt to use this tool immediately after learning Quartus II. Instead, I only had the chance to pick up this tool after about one year being an Altera user. It is worth every moment to learn and pick up this tool as it makes your debugging process simpler and a lot faster. Unlike Xilinx’s ChipScope Pro, you don’t need to install the SignalTap II tool separately. It comes together with Quartus II and it is available after the Quartus II installation is done.

Last but not least, thanks to Altera that the SignalTap II is FREE!!

Friday, May 19, 2006

USB-Blaster vs Platform Cable USB

Both USB-Blaster and Platform Cable USB are the USB download cables provided by Altera and Xilinx, respectively. Most of time, the download cable is a necessity while developing and debugging your design in the FPGA. You need them to download the FPGA configuration bitstream through JTAG or Passive/Slave serial mode, to program the CPLD, to program the configuration device, to download your firmware into the soft processor and to tap the signals inside the FPGA through the FPGA embedded logic analyzer. Both of them are able to achieve all the above-mentioned purposes. But what is the main difference between them? The SELLING PRICE!!! The USB-Blaster costs USD$300 while the Platform Cable USB only costs half the price of the USB-Blaster, which is USD$149. This is really killing me because sometimes I need to use more than one download cable at the same time when dealing with multi-FPGA environment. Why can’t the Altera USB-Blaster at least cost the same like the Xilinx Platform Cable USB? In fact, Xilinx Platform Cable USB has even more features than USB-Blaster such as programming the configuration clock frequency. The USB-Blaster operates at USB full speed, which is 12Mbps, while the Platform Cable USB can operate at USB high speed!

Frankly speaking, the download cable should cost as cheap as possible by the FPGA vendors because they should be making money from selling their FPGA and CPLD devices, not from selling the download cables. Similar to the Quartus II and ISE web edition software tool, the download cable should just be a marketing tool to help promote the usage of FPGA or CPLD solutions! Imagine if I am a newbie who want to learn to use FPGA or CPLD on my own, it doesn’t make sense for me to buy a tool that is much much more expensive than a single low-cost FPGA/CPLD device.

Anyway, just for your reference, I also compare the cost of download cables that use the PC parallel port interface which are Altera ByteBlaster II, USD$150 and Xilinx Parallel Cable IV, USD$95. Once again, Xilinx is the winner when it comes to the price war. Is this the reason Xilinx being the market leader? Well, you know better.

// Disclaimer: All the price stated above are extracted from Altera Buy On-Line and Xilinx Online Store websites at the posting time and may change from time to time in future.