Quartus II Synthesis Error During Compilation

If you are seeing the following error message and wondering what is wrong with your System Verilog syntax, then, you have come to the right place.  I believe you are using dual dimensional input and/or output in the module port list like shown in the template below.  The truth is there might be nothing wrong with your code, you just need to add the System Verilog file into the Quartus II project. 

module SubModule

(
  input                   clk,
  input                   reset,
  input[15:0]          input_port[0:3],
  output reg[15:0]  output_port[0:3]
);

endmodule

To add this file to your Quartus II project, simply go to Project menu and choose “Add/Remove Files in Project…”.  The rest of the steps should be quite straight forward for you.  Just choose the file and add it in the project.  Then, recompile your Quartus II project.  After that, this synthesis error will disappear.  Before doing this step, if you right-click on the error message and choose Help, it will show you the Quartus II help like the shown in the link below but to me this help content doesn’t help at all.

http://quartushelp.altera.com/17.0/index.htm#msgs/msgs/evrfx_sv_aggregate_port_connection_requires_module.htm

I need to write this down to keep reminding myself not to fall into the same trap again.  Sometimes, it could just take hours to realize about this.  As far as I know, this happens to the latest Quartus II version 17.0 (latest as of today) and also earlier Quartus II versions.

Here is the synthesis error message displayed in the Quartus II message window.

ID:10703 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance "<string>" because the instance has no module binding

Hope this helps you.