Can a PLL lock itself if I connect a PLL output clock to the PLL input clock on a PCB and both the PLL multiplication and division value is set to 1? I expected the answer is no, of course. But the curiosity kills sometimes. So, I went ahead and did the simple test.
I was using a Cyclone II device. Surprisingly, I saw the PLL locked output signal went high. However, the output signal frequency wasn't the expected frequency (10MHz). I probed at the PLL output clock (which was also connected to the PLL input clock signal), it showed about 420kHz.
So, what is the conclusion of this story? Nothing.
